The requirements of a computer memory vary widely as to capacity, speed, data bus width, and the like, depending on the application of the computer. It has been customary for manufacturers of general purpose computers to provide modular memory subsystems. The memory subsystem includes a number of slots, or connectors, for memory modules. Memory modules may be mounted in some or all of the slots, depending on the application. The memory modules may vary as to capacity, operating speed, data bus width, etc.
A typical computer utilizes a memory controller for converting a memory address supplied by the CPU into the required address and control signals for accessing a particular memory location. The typical memory controller generates row address strobe, column address strobe and write enable signals. The memory controller is typically implemented in one or more large scale integrated circuits. When the memory is modular, the memory controller and the CPU must receive information which defines the memory configuration in order to supply the required address and control signals to the memory modules that are present in the system. It is thus customary that each memory module provides a number of presence detect codes, or presence detect bits, at its connector. The presence detect bits include information as to the memory module capacity, DRAM device speed, etc. A memory configuration is determined from the presence detect bits. An example of a memory module that provides presence detect bits is a single in-line memory module (SIMM).
A large number of presence detect bits must be handled by the memory controller. A typical memory subsystem may include up to 8 memory modules, each of which generates 6 presence detect bits, totaling 48 presence detect bits. This information must be input to the memory controller integrated circuit, where the number of I/O pins is limited. In prior art systems, presence detect bits have typically been latched in parallel because they are available in parallel from the memory modules.
In existing memory subsystems, memory modules may be utilized in pairs to achieve a wide data bus. For example, many computer systems require a 64 bit memory data bus, whereas standard memory modules are available with a 32 bit data bus. It is thus necessary that the memory modules be installed in pairs to achieve the 64 bit data bus. In this case, the memory modules of each pair must be identical. The computer system must be capable of determining when a user inadvertently installs different memory modules as a pair. In prior art systems, determining memory module pair mismatches has been performed by the system software. This approach has the disadvantages of requiring software intervention, which takes time, and requiring a larger number of registers in the system software in order to identify memory module mismatches.